Invention Grant
- Patent Title: Method of forming stress memorization layer on backside of semiconductor substrate and semiconductor device thereof
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Application No.: US16542667Application Date: 2019-08-16
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Publication No.: US11444153B2Publication Date: 2022-09-13
- Inventor: Qintao Zhang , Wei Zou
- Applicant: APPLIED Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED Materials, Inc.
- Current Assignee: APPLIED Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDB Firm PLLC
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/265
Abstract:
Embodiments herein are directed to methods and devices having a stress memorization layer along a side of a substrate. In some embodiments, a method may include providing a substrate having a first main side opposite a second main side, implanting the second main side of the substrate to form an amorphous implant area, forming a stress liner over the second main side of the substrate, and annealing the stress liner to form a stress memorization layer in the amorphous implant area.
Public/Granted literature
- US20210050411A1 SEMICONDUCTOR SUBSTRATE INCLUDING STRESS MEMORIZATION LAYER Public/Granted day:2021-02-18
Information query
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