Invention Grant
- Patent Title: Vertical memory device with tri-layer channel
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Application No.: US16957579Application Date: 2018-11-19
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Publication No.: US11444100B2Publication Date: 2022-09-13
- Inventor: Tae Whan Kim , Jun Gyu Lee , Hyun Soo Jung
- Applicant: Industry-University Cooperation Foundation Hanyang University
- Applicant Address: KR Seoul
- Assignee: Industry-University Cooperation Foundation Hanyang University
- Current Assignee: Industry-University Cooperation Foundation Hanyang University
- Current Assignee Address: KR Seoul
- Agency: Novick, Kim & Lee, PLLC
- Agent Jae Youn Kim
- Priority: KR10-2018-0065885 20180608
- International Application: PCT/KR2018/014191 WO 20181119
- International Announcement: WO2019/235701 WO 20191212
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11556 ; H01L27/1157

Abstract:
A vertical memory device and a method of fabricating the same are proposed. The vertical memory device includes a gate stack structure in which gates and interlayer insulating layers for insulating the gates are alternately laminated on a substrate and multiple memory cell areas and inter-memory cell areas are divided in a first direction perpendicular to the substrate; a channel structure extending in the first direction from the substrate to penetrate the gate stack structure; and charge storage elements disposed between the gate stack structure and the channel structure and sequentially formed to be embedded in the gate stack structure.
Public/Granted literature
- US20200328229A1 VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2020-10-15
Information query
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