Invention Grant
- Patent Title: Process of realization of an area of individualization of an integrated circuit
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Application No.: US17216794Application Date: 2021-03-30
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Publication No.: US11444041B2Publication Date: 2022-09-13
- Inventor: Hubert Teyssedre , Stefan Landis , Michael May
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR2003110 20200330
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/768

Abstract:
A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.
Public/Granted literature
- US20210375794A1 PROCESS OF REALIZATION OF AN AREA OF INDIVIDUALIZATION OF AN INTEGRATED CIRCUIT Public/Granted day:2021-12-02
Information query
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