Invention Grant
- Patent Title: Methods of forming a package substrate
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Application No.: US16803361Application Date: 2020-02-27
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Publication No.: US11443970B2Publication Date: 2022-09-13
- Inventor: Manohar S. Konchady , Tao Wu , Mihir K. Roy , Wei-Lun K. Jen , Yi Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/683
- IPC: H01L21/683 ; H01L23/538 ; H01L23/498

Abstract:
A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
Information query
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