Invention Grant
- Patent Title: Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning
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Application No.: US16682607Application Date: 2019-11-13
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Publication No.: US11443953B2Publication Date: 2022-09-13
- Inventor: Kandabara N. Tapily , Anton deVilliers , Gerrit J. Leusink
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469 ; H01L21/311 ; H01L21/02

Abstract:
A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.
Public/Granted literature
- US20200152473A1 METHOD FOR FORMING AND USING STRESS-TUNED SILICON OXIDE FILMS IN SEMICONDUCTOR DEVICE PATTERNING Public/Granted day:2020-05-14
Information query
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