Invention Grant
- Patent Title: Package with substrate comprising variable thickness solder resist layer
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Application No.: US17149498Application Date: 2021-01-14
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Publication No.: US11439008B2Publication Date: 2022-09-06
- Inventor: Kun Fang , Jaehyun Yeon , Suhyung Hwang , Hyunchul Cho , Boyu Tseng
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP/Qualcomm
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H01L21/48 ; H05K1/02

Abstract:
A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.
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