Invention Grant
- Patent Title: Stacked transistor bit-cell for magnetic random access memory
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Application No.: US16128422Application Date: 2018-09-11
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Publication No.: US11411047B2Publication Date: 2022-08-09
- Inventor: Sasikanth Manipatruni , Christopher Wiegand , Tanay Gosavi , Ian Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L27/22
- IPC: H01L27/22 ; H01L43/10 ; H01L43/02 ; H01L27/12

Abstract:
An apparatus is provided which comprises: a magnetic junction (e.g., a magnetic tunneling junction or spin valve). The apparatus further includes a structure (e.g., an interconnect) comprising spin orbit material, the structure adjacent to the magnetic junction; first and second transistors. The first transistor is coupled to a bit-line and a first word-line, wherein the first transistor is adjacent to the magnetic junction. The second transistor is coupled to a first select-line and a second word-line, wherein the second transistor is adjacent to the structure, wherein the interconnect is coupled to a second select-line, and wherein the magnetic junction is between the first and second transistors.
Public/Granted literature
- US20200083286A1 STACKED TRANSISTOR BIT-CELL FOR MAGNETIC RANDOM ACCESS MEMORY Public/Granted day:2020-03-12
Information query
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