Invention Grant
- Patent Title: Increased memory access parallelism using parity
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Application No.: US17136863Application Date: 2020-12-29
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Publication No.: US11409600B2Publication Date: 2022-08-09
- Inventor: Qing Liang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F12/1009 ; G06F3/06

Abstract:
Disclosed in some examples are memory devices which increase a parallelism of host operations of a memory device. While a first block of data from a first stripe in a first memory die is being read, blocks of data belonging to a second stripe stored in memory dies other than the first memory die are concurrently read. This includes reading the parity value of the second stripe. The parity data, along with the blocks of data from the second stripe from dies other than the first die are then used to determine the block of data of the second stripe stored in the first memory die without actually reading the value from the block in the first memory die. This reconstruction may be done in parallel with additional read operations for other data performed on the first die.
Public/Granted literature
- US20210200633A1 INCREASED MEMORY ACCESS PARALLELISM USING PARITY Public/Granted day:2021-07-01
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