Invention Grant
- Patent Title: Determining critical timing paths in a superconducting circuit design
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Application No.: US16518668Application Date: 2019-07-22
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Publication No.: US11380835B2Publication Date: 2022-07-05
- Inventor: Janet L. Schneider , Paul Accisano , Mark G. Kupferschmidt , Kenneth Reneris
- Applicant: Microsoft Technology Licensing, LLC
- Applicant Address: US WA Redmond
- Assignee: Microsoft Technology Licensing, LLC
- Current Assignee: Microsoft Technology Licensing, LLC
- Current Assignee Address: US WA Redmond
- Agency: Singh Law, PLLC
- Agent Ranjeev Singh
- Main IPC: H01L39/22
- IPC: H01L39/22 ; H03K19/195 ; H03K19/20 ; H01L39/02 ; H03K3/38

Abstract:
Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.
Public/Granted literature
- US20220180038A1 DETERMINING CRITICAL TIMING PATHS IN A SUPERCONDUCTING CIRCUIT DESIGN Public/Granted day:2022-06-09
Information query
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