Addressing an emissive display having pixels arranged into rows and columns. A first clock signal is received at an address select input of a first row of the display. Data signals are received at data signal inputs of the first row of the display, each of the received data signals corresponding to a column of the display. When the first clock signal is active at the address select input, the data signals are output to corresponding drivers of light emitting semi-conductors of the first row and via corresponding data signal outputs of the first row. The data signals are received from the data signal outputs of the first row at a first row of shift registers. A second clock signal is received at the first row of shift registers. When the second clock signal is active, the data signals are output from the first row of shift registers.