A data processing apparatus (2) operates in a first mode of operation having a first set of processing circuitry (8, 12, 18, 20, 22) ready to perform processing operations and in a second mode of operation having a second set of processing circuitry (8, 12, 14, 18, 20, 22, 24) ready to perform processing operations. A first proper subset (32) of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. A second proper subset (34) of program instructions within the instruction set are required to be processed by the processor operating in the second mode. Processing circuitry (14, 24) which is inactive in a mode of operation may be placed into a low power state.