Invention Grant
- Patent Title: Source/drain recess etch stop layers and bottom wide-gap cap for III-V MOSFETs
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Application No.: US16316337Application Date: 2016-09-26
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Publication No.: US11367789B2Publication Date: 2022-06-21
- Inventor: Cheng-Ying Huang , Willy Rachmady , Matthew V. Metz , Gilbert Dewey , Jack T. Kavalieros , Sean T. Ma , Harold Kennel
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/053831 WO 20160926
- International Announcement: WO2018/057043 WO 20180329
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L29/20 ; H01L29/417 ; H01L29/66 ; H01L29/786 ; H01L29/778 ; H01L29/10 ; H01L29/775 ; H01L29/06 ; H01L29/423 ; B82Y10/00
Abstract:
A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.
Public/Granted literature
- US20190296145A1 SOURCE/DRAIN RECESS ETCH STOP LAYERS AND BOTTOM WIDE-GAP CAP FOR III-V MOSFETS Public/Granted day:2019-09-26
Information query
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