- Patent Title: Semiconductor integrated circuit and withstand voltage test method
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Application No.: US16794639Application Date: 2020-02-19
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Publication No.: US11367694B2Publication Date: 2022-06-21
- Inventor: Kenichi Murakoshi , Kimitsugu Yoshikawa , Tatsuya Ishida
- Applicant: SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO. LTD.
- Applicant Address: CN Shenzhen
- Assignee: SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO. LTD.
- Current Assignee: SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO. LTD.
- Current Assignee Address: CN Shenzhen
- Agency: ScienBiziP, P.C.
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L21/82 ; H01L23/522 ; G01R31/28 ; H01L23/31 ; H01L23/00
Abstract:
A voltage application region and a voltage applying pad form withstand voltage measuring wiring lines insulated from each other and different from each other by connecting a seal ring and a relay region through a via, and the withstand voltage measuring wiring lines different from each other are configured to apply a voltage between insulated seal rings provided on wiring layers adjacent to each other by applying a voltage between the voltage application region and the voltage applying pad.
Public/Granted literature
- US20200266157A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND WITHSTAND VOLTAGE TEST METHOD Public/Granted day:2020-08-20
Information query
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