Invention Grant
- Patent Title: Integration of silicon channel nanostructures and silicon-germanium channel nanostructures
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Application No.: US16910488Application Date: 2020-06-24
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Publication No.: US11296081B2Publication Date: 2022-04-05
- Inventor: Shi Ning Ju , Kuo-Cheng Chiang , Chih-Hao Wang , Kuan-Lun Cheng , Guan-Lin Chen
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: The Marbury Law Group, PLLC
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/417 ; H01L29/78 ; H01L29/16 ; H01L29/06 ; H01L29/66

Abstract:
A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
Public/Granted literature
- US20210407993A1 INTEGRATION OF SILICON CHANNEL NANOSTRUCTURES AND SILICON-GERMANIUM CHANNEL NANOSTRUCTURES Public/Granted day:2021-12-30
Information query
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