- Patent Title: SRAM with local bit line, input/output circuit, and global bit line
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Application No.: US17027209Application Date: 2020-09-21
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Publication No.: US11295791B2Publication Date: 2022-04-05
- Inventor: Atul Katoch , Ali Taghvaei
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Merchant & Gould P.C.
- Main IPC: G11C7/12
- IPC: G11C7/12 ; G11C11/4091 ; G11C16/04 ; G11C7/10 ; G11C7/06 ; G11C7/18 ; G11C11/419
Abstract:
A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.
Public/Granted literature
- US20210005232A1 SRAM WITH LOCAL BIT LINE, INPUT/OUTPUT CIRCUIT, AND GLOBAL BIT LINE Public/Granted day:2021-01-07
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