Invention Grant
- Patent Title: Method of correcting errors in a memory array and method of screening weak bits in the same
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Application No.: US16786795Application Date: 2020-02-10
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Publication No.: US11294764B2Publication Date: 2022-04-05
- Inventor: Yu-Der Chih , Chia-Fu Lee , Chien-Yin Liu , Yi-Chun Shih , Kuan-Chun Chen , Hsueh-Chih Yang , Shih-Lien Linus Lu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/29 ; H03M13/15 ; H03M13/19 ; G11C29/42

Abstract:
A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.
Public/Granted literature
- US20200174883A1 METHOD OF CORRECTING ERRORS IN A MEMORY ARRAY AND METHOD OF SCREENING WEAK BITS IN THE SAME Public/Granted day:2020-06-04
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