According to one embodiment, a semiconductor memory device includes a stacked body disposed in a first tier, the stacked body including a plurality of conductive layers stacked via an insulating layer; a first pillar that extends in the stacked body in a stacking direction of the stacked body; a first upper structure disposed in a second tier upper than the first tier; and a misalignment mark for inspecting misalignment between the first tier and the second tier, wherein the misalignment mark includes a second pillar that extends the first tier of the misalignment inspection region in the stacking direction, and a second upper structure disposed in the second tier of the misalignment inspection region and superposed on the second pillar in a top view.