Invention Grant
- Patent Title: Trap-rich layer in a high-resistivity semiconductor layer
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Application No.: US16807453Application Date: 2020-03-03
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Publication No.: US11271077B2Publication Date: 2022-03-08
- Inventor: Anthony K. Stamper , Vibhor Jain , John J. Pekarik , Steven M. Shank , John J. Ellis-Monaghan
- Applicant: GLOBALFOUNDRIES U.S. Inc.
- Applicant Address: US CA Santa Clara
- Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Thompson Hine LLP
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L21/76 ; H01L29/06 ; H01L29/04 ; H01L21/762 ; H01L27/102 ; H01L29/737 ; H01L27/12 ; H01L21/324 ; H01L29/32

Abstract:
Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.
Public/Granted literature
- US20210280672A1 TRAP-RICH LAYER IN A HIGH-RESISTIVITY SEMICONDUCTOR LAYER Public/Granted day:2021-09-09
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