Invention Grant
- Patent Title: Laminate stacked on die for high voltage isolation capacitor
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Application No.: US16806362Application Date: 2020-03-02
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Publication No.: US11270930B2Publication Date: 2022-03-08
- Inventor: Thomas Dyer Bonifield
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48 ; H01L23/00 ; H01L23/64 ; H01L49/02 ; H01L25/065 ; H01L25/00

Abstract:
An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.
Public/Granted literature
- US11139227B2 Laminate stacked on die for high voltage isolation capacitor Public/Granted day:2021-10-05
Information query
IPC分类: