• Patent Title: Processing circuit using delay element coupled between control terminal and connection terminal of input transistor for hold time violation immunity
  • Application No.: US17151672
    Application Date: 2021-01-19
  • Publication No.: US11264974B2
    Publication Date: 2022-03-01
  • Inventor: Jen-Hang Yang
  • Applicant: MEDIATEK INC.
  • Applicant Address: TW Hsin-Chu
  • Assignee: MEDIATEK INC.
  • Current Assignee: MEDIATEK INC.
  • Current Assignee Address: TW Hsin-Chu
  • Agent Winston Hsu
  • Main IPC: H03K3/037
  • IPC: H03K3/037
Processing circuit using delay element coupled between control terminal and connection terminal of input transistor for hold time violation immunity
Abstract:
A processing circuit includes an input circuit and a follow-up circuit. The input circuit includes a first transistor, a second transistor, and a delay element. The first transistor has a control terminal, a first connection terminal, and a second connection terminal. The control terminal of the first transistor is arranged to receive a data signal. A first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, and a control terminal of the second transistor is arranged to receive a first non-data signal. The delay element is coupled between the control terminal and the second connection terminal of the first transistor. A data input is received at an input node of the follow-up circuit, and the input node of the follow-up circuit is coupled to the second connection terminal of the second transistor.
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