Invention Grant
- Patent Title: Transistor with buried p-field termination region
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Application No.: US16853072Application Date: 2020-04-20
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Publication No.: US11264496B2Publication Date: 2022-03-01
- Inventor: Noel Hoilien
- Applicant: Polar Semiconductor, LLC
- Applicant Address: US MN Bloomington
- Assignee: Polar Semiconductor, LLC
- Current Assignee: Polar Semiconductor, LLC
- Current Assignee Address: US MN Bloomington
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/78 ; H01L21/02 ; H01L29/66

Abstract:
In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.
Public/Granted literature
- US20210328054A1 TRANSISTOR WITH BURIED P-FIELD TERMINATION REGION Public/Granted day:2021-10-21
Information query
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