Invention Grant
- Patent Title: Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions
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Application No.: US16570482Application Date: 2019-09-13
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Publication No.: US11264471B2Publication Date: 2022-03-01
- Inventor: Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/66 ; H01L29/808 ; H01L29/06

Abstract:
A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.
Public/Granted literature
- US20200006507A1 JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET) HAVING SOURCE/DRAIN AND GATE ISOLATION REGIONS Public/Granted day:2020-01-02
Information query
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