Invention Grant
- Patent Title: Isolation regions for reduced junction leakage
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Application No.: US16855914Application Date: 2020-04-22
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Publication No.: US11264456B2Publication Date: 2022-03-01
- Inventor: Gulbagh Singh , Hsin-Chi Chen , Kun-Tsang Chuang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/762 ; H01L21/8234 ; H01L21/306 ; H01L21/02 ; H01L21/768

Abstract:
The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.
Public/Granted literature
- US20200251554A1 ISOLATION REGIONS FOR REDUCED JUNCTION LEAKAGE Public/Granted day:2020-08-06
Information query
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