Invention Grant
- Patent Title: Chip package with connection portion that passes through an encapsulation portion
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Application No.: US16636638Application Date: 2018-08-03
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Publication No.: US11264330B2Publication Date: 2022-03-01
- Inventor: Yongtae Kwon , Eung Ju Lee , Yong Woon Yeo , Yun Mook Park , Hyo Young Kim , Jun Kyu Lee , Seok Hwi Cheon
- Applicant: NEPES CO., LTD.
- Applicant Address: KR Chungcheongbuk-do
- Assignee: NEPES CO., LTD.
- Current Assignee: NEPES CO., LTD.
- Current Assignee Address: KR Chungcheongbuk-do
- Agency: Renaissance IP Law Group LLP
- Priority: KR10-2017-0098911 20170804,KR10-2017-0126263 20170928,KR10-2017-0126334 20170928,KR10-2017-0126398 20170928,KR10-2018-0081717 20180713
- International Application: PCT/KR2018/008816 WO 20180803
- International Announcement: WO2019/027278 WO 20190207
- Main IPC: H01L23/538
- IPC: H01L23/538 ; G06K9/00 ; H01L23/31

Abstract:
Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer without using a separate insulating layer formed on the molding layer as in the conventional art.
Public/Granted literature
- US20210151379A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-05-20
Information query
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