Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is delayed read disturb which results from a low word line voltage during idle periods of the memory device. In one aspect, periodic refresh operations are optimized based on factors such as a number of bits per cell in the block and number of program-erase (P-E) cycles. For example, at high P-E cycles, the amplitude of a refresh voltage for a single-level cell (SLC) block can be 0 V or lower while the amplitude of a refresh voltage for a multi-level cell (MLC) block can be an intermediate voltage between 0 V and a pass voltage.