Invention Grant
- Patent Title: Host-resident translation layer validity check
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Application No.: US16054072Application Date: 2018-08-03
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Publication No.: US11263124B2Publication Date: 2022-03-01
- Inventor: David Aaron Palmer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/0873 ; G06F12/0871
Abstract:
Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
Public/Granted literature
- US20200042436A1 HOST-RESIDENT TRANSLATION LAYER VALIDITY CHECK Public/Granted day:2020-02-06
Information query
