A method of enhancing SAR ADC conversion rate by employing a new value shifted capacitor DAC. The value shifted capacitor DAC decreases largest capacitor to improve the reference voltage settling. The reduction of capacitor is added back onto the smaller capacitor DAC to maintain the same total capacitor value. The binary search outputs are re-combined and processed to produce final binary ADC outputs. The overhead of using value shifted capacitor DAC is the extra latency needed for re-combined logic.