Invention Grant
- Patent Title: Stress reduction apparatus and method
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Application No.: US16568501Application Date: 2019-09-12
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Publication No.: US11244940B2Publication Date: 2022-02-08
- Inventor: Yao-Chun Chuang , Yu-Chen Hsu , Hao Chun Liu , Chita Chuang , Chen-Cheng Kuo , Chen-Shien Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/00 ; H01L21/56 ; H01L23/31 ; H01L25/065

Abstract:
A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
Public/Granted literature
- US20200006311A1 Stress Reduction Apparatus and Method Public/Granted day:2020-01-02
Information query
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