Apparatus and method for reducing output skew and transition delay of level shifter
Abstract:
An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vol+ and Vol−; and an output alignment circuit configured to output voltages Vo+ and Vo− that are triggered by an edge of a combination of Vol+ and Vol−, and where Vo+ and Vo− are set by high states of Vol+ and Vol− prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vol+ and Vol−; and outputting, by an output alignment circuit, voltages Vo+ and Vo− that are triggered by an edge of a combination of Vol+ and Vol−, and where Vo+ and Vo− are set by high states of Vol+ and Vol− prior to a transition on an input of the level-shifter circuit.
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