Invention Grant
- Patent Title: Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods
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Application No.: US17002486Application Date: 2020-08-25
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Publication No.: US11222846B1Publication Date: 2022-01-11
- Inventor: Sunil Sharma , Rahul Biradar , Sonia Ghosh
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: QUALCOMM Incorporated
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L27/11 ; H01L21/8238 ; H01L21/768 ; H01L23/522

Abstract:
Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.
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