Invention Grant
- Patent Title: Semiconductor device, memory controller, and memory accessing method
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Application No.: US16685178Application Date: 2019-11-15
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Publication No.: US11221789B2Publication Date: 2022-01-11
- Inventor: Sho Yamanaka , Nobuhiko Honda , Takahiro Irita
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2018-240740 20181225
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10

Abstract:
When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.
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