Invention Grant
- Patent Title: Connection structure for stacked substrates
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Application No.: US16587539Application Date: 2019-09-30
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Publication No.: US11217553B2Publication Date: 2022-01-04
- Inventor: Hsiang-Jen Tseng , Wei-Yu Chen , Ting-Wei Chiang , Li-Chun Tien
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/528 ; H01L25/00 ; H01L21/768 ; H01L23/48 ; H01L21/822 ; H01L27/06 ; H01L23/535 ; H01L21/74 ; H01L25/07 ; H01L27/118 ; H01L23/522 ; H01L23/532

Abstract:
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having a first pair of sidewalls extending in a first direction and a second pair of sidewalls. One or more of the second pair of sidewalls extend past the first pair of sidewalls in a second direction that intersects the first direction as viewed from a top-view of the semiconductor substrate. The first pair of sidewalls and the second pair of sidewalls define one or more trenches within the semiconductor substrate. An interconnecting structure including a conductive material is disposed within the one or more trenches in the semiconductor substrate. The interconnecting structure continuously extends completely through the semiconductor substrate.
Public/Granted literature
- US20200027853A1 CONNECTION STRUCTURE FOR STACKED SUBSTRATES Public/Granted day:2020-01-23
Information query
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