Memory devices with distributed block select for a vertical string driver tile architecture
Abstract:
Memory devices are disclosed. A memory device may include multiple pairs of tiles. At least some of the pairs of tiles may include a block select circuit. At least one portion of the block select circuit within a first pair of tiles of the multiple pairs of tiles is offset from at least one other portion of the block select circuit within a second pair of tiles of the multiple pairs of tiles. Also, at least one pair of tiles of the multiple pair of tiles may include an associated vertical string driver offset from each of a first tile and a second tile of an associated pair of tiles.
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