An operation method of a system-on-chip (SoC) that controls a memory device includes transmitting a first mode register write (MRW) command to the memory device through command/address (CA) lines, transmitting a second MRW command including a specific pattern to the memory device through the CA lines, transmitting a first mode register read (MRR) command for reading the specific pattern to the memory device through the CA lines, capturing the specific pattern received through data lines from the memory device based on an SoC reference voltage, adjusting the SoC reference voltage based on the captured specific pattern, transmitting a second MRR command to the memory device through the CA lines, capturing data signals received from the memory device through the data lines based on the adjusted SoC reference voltage, and performing a plurality of training operations on the memory device after adjusting the SoC reference voltage.