The array substrate comprises: a substrate including a first region, a second region, and a third region; a first metal layer is disposed on the substrate and forms a gate metal and a common line; a first insulating layer is disposed on the substrate and the first metal layer; a second metal layer is disposed on the first insulating layer and forms a source/drain metal; a second insulating layer is disposed on the first insulating layer and the second metal layer; and a third metal layer is disposed on the second insulating layer and forms a voltage signal line.