Invention Grant
- Patent Title: Techniques for setting a 2-level auto-close timer to access a memory device
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Application No.: US16584612Application Date: 2019-09-26
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Publication No.: US11216386B2Publication Date: 2022-01-04
- Inventor: Vivek Kozhikkottu , Suresh Chittor , Esha Choukse , Shankar Ganesh Ramasubramanian
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1045 ; G06F12/06 ; G06F11/30 ; G06F13/16 ; G06F12/02

Abstract:
Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.
Public/Granted literature
- US20200019513A1 TECHNIQUES FOR SETTING A 2-LEVEL AUTO-CLOSE TIMER TO ACCESS A MEMORY DEVICE Public/Granted day:2020-01-16
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