Invention Grant
- Patent Title: Semiconductor device with gate-all-around (GAA) FETs having inner insulating spacers
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Application No.: US16655079Application Date: 2019-10-16
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Publication No.: US11139381B2Publication Date: 2021-10-05
- Inventor: Kuo-Cheng Ching , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L27/092 ; H01L29/04 ; H01L29/165 ; H01L29/78 ; H01L29/786 ; H01L29/66

Abstract:
In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
Public/Granted literature
- US20200052084A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE Public/Granted day:2020-02-13
Information query
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