Invention Grant
- Patent Title: Semiconductor device and method of manufacturing semiconductor device
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Application No.: US16559552Application Date: 2019-09-03
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Publication No.: US11139208B2Publication Date: 2021-10-05
- Inventor: Takanobu Ono , Tsutomu Fujita , Ippei Kume , Akira Tomono
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JPJP2019-047449 20190314
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/31 ; H01L21/56 ; H01L21/268 ; H01L21/304

Abstract:
A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip.
Public/Granted literature
- US20200294856A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2020-09-17
Information query
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