Voltage stabilization circuit, control method, and display device
Abstract:
A voltage stabilization circuit, a control method, and a display device are provided. The circuit includes first transistor, second transistor, and third transistor. A source of the first transistor is electrically connected to a drain of the second transistor and a gate of the third transistor, a drain of the first transistor is electrically connected to a first control output terminal of a power management integrated circuit, a gate of the first transistor is electrically connected to a second control output terminal of the power management integrated circuit, a gate of the second transistor is electrically connected to the second control output terminal of the power management integrated circuit, and a drain of the third transistor is electrically connected to a first level terminal for connecting to a display panel. This solves issues of VSSG potential drift caused by transistor aging and further guarantees normal operation of the display panel.
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