Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.