Invention Grant
- Patent Title: Isolation structure for stacked vertical transistors
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Application No.: US16386945Application Date: 2019-04-17
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Publication No.: US11081546B2Publication Date: 2021-08-03
- Inventor: Juntao Li , Kangguo Cheng , Chen Zhang , Zhenxing Bi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Erik Johnson
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/66 ; H01L29/78 ; H01L21/3065 ; H01L29/06 ; H01L27/092 ; H01L29/165

Abstract:
A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.
Public/Granted literature
- US20200335581A1 ISOLATION STRUCTURE FOR STACKED VERTICAL TRANSISTORS Public/Granted day:2020-10-22
Information query
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