Invention Grant
- Patent Title: Apparatuses and methods for arranging through-silicon vias and pads in a semiconductor device
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Application No.: US16235645Application Date: 2018-12-28
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Publication No.: US11081467B2Publication Date: 2021-08-03
- Inventor: Tomohiro Kitano
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/66 ; H01L23/48 ; H01L23/532 ; H01L23/00 ; H01L21/768 ; H01L25/00

Abstract:
A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.
Public/Granted literature
- US20200212008A1 APPARATUSES AND METHODS FOR ARRANGING THROUGH-SILICON VIAS AND PADS IN A SEMICONDUCTOR DEVICE Public/Granted day:2020-07-02
Information query
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