The memory includes a first descriptor area and a first data area corresponding to the first OS, and a second descriptor area and a second data area corresponding to the second OS. The second processor stores the first transmission instruction information corresponding to the transmission data stored in the second data area in the second descriptor area and transmits a first update notification of the second descriptor area to the first processor. In response to the first update notification, the first processor reads the first transmission instruction information stored in the second descriptor area and stores the first transmission instruction information in the first descriptor area. The communication circuit controlled by the first processor performs transmission process of transmission data stored in the second data area based on the first transmission instruction information stored in the first descriptor area.