Invention Grant
- Patent Title: Spacer for dual epi CMOS devices
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Application No.: US16356225Application Date: 2019-03-18
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Publication No.: US11031396B2Publication Date: 2021-06-08
- Inventor: Soon-Cheon Seo
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent L. Jeffrey Kelly
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L21/311 ; H01L21/02 ; H01L21/84

Abstract:
A method for making a semiconductor includes patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor, and etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.
Public/Granted literature
- US20190214389A1 SPACER FOR DUAL EPI CMOS DEVICES Public/Granted day:2019-07-11
Information query
IPC分类: