Invention Grant
- Patent Title: Methods of compensating for misalignment of bonded semiconductor wafers
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Application No.: US16294782Application Date: 2019-03-06
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Publication No.: US11031374B2Publication Date: 2021-06-08
- Inventor: Mitsunari Sukekawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/18 ; H01L25/00

Abstract:
Some embodiments include a method in which a first semiconductor wafer and a second semiconductor wafer are bonded with each other. The first semiconductor wafer includes a memory cell array, and the second semiconductor wafer includes a circuit to access the memory cell array. After the bonding, contacts are formed to be associated with the first semiconductor wafer. The contacts are for electrical connections between the first and second semiconductor wafers. The contacts are linked with reference positions, with each of the contacts being linked with an associated one of the reference positions. Each of the contacts is shifted from its associated one of the reference positions to absorb a bonding alignment error between the first and second semiconductor wafers.
Public/Granted literature
- US20200286859A1 Methods of Compensating for Misalignment of Bonded Semiconductor Wafers Public/Granted day:2020-09-10
Information query
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