Invention Grant
- Patent Title: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
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Application No.: US16577645Application Date: 2019-09-20
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Publication No.: US11031363B2Publication Date: 2021-06-08
- Inventor: Hsien-Wei Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/10 ; H01L23/31 ; G06F30/39 ; H01L25/065

Abstract:
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.
Public/Granted literature
- US20200013742A1 Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices Public/Granted day:2020-01-09
Information query
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