Invention Grant
- Patent Title: Semiconductor package and method
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Application No.: US15925174Application Date: 2018-03-19
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Publication No.: US11031342B2Publication Date: 2021-06-08
- Inventor: Shih-Hao Tseng , Hung-Jui Kuo , Ming-Che Ho
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/311 ; H01L21/56 ; H01L21/768 ; H01L23/31 ; H01L23/538 ; H01L23/00 ; H01L21/288 ; H01L21/683 ; H01L21/321 ; H01L25/10

Abstract:
In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.
Public/Granted literature
- US20190148302A1 Semiconductor Package and Method Public/Granted day:2019-05-16
Information query
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