Invention Grant
- Patent Title: Forming dual metallization interconnect structures in single metallization level
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Application No.: US16445428Application Date: 2019-06-19
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Publication No.: US11031337B2Publication Date: 2021-06-08
- Inventor: Hari P. Amanapu , Charan V. Surisetty , Raghuveer R. Patlolla
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent James Nock
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L23/528

Abstract:
Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.
Public/Granted literature
- US20190311986A1 FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL Public/Granted day:2019-10-10
Information query
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