A memory device may include a clock dividing circuit suitable for generating a plurality of internal clocks by dividing an external clock, a mode decision circuit suitable for determining an operation mode according to an input time point of a read command based on the internal clocks, a clock arranging circuit suitable for arranging the internal clocks in an order determined according to the operation mode, and outputting the arranged clocks as a plurality of data output clocks, and a data arranging circuit suitable for arranging read data according to the operation mode, and outputting the arranged data in response to the data output clocks.