A semiconductor structure is provided. The semiconductor structure includes a substrate and a plurality of memory cells arranged in a cell array over the substrate. Each of the memory cells includes a latch circuit, a pass-gate transistor, and an isolation transistor. The latch circuit is formed by two cross-coupled inverters. The pass-gate transistor is coupled between an output terminal of the latch circuit and a bit line. The isolation transistor includes a drain and a gate, both coupled to the output terminal of the latch circuit, and a source that is floating. A first gate length of the isolation transistor is greater than a second gate length of the pass-gate transistor and a plurality of transistors within the latch circuit.